Hi, I'm Divyanshu Jain - Silicon Engineer at Google
I'm driven by optimizing silicon chip performance through meticulous timing constraint engineering. I thrive in collaborative environments at leading tech companies, leveraging my scripting and flow development skills to solve complex challenges and drive impactful results.
At a glance
Curated signals on strengths, focus areas, and how they can help.
Interned at Qualcomm, gaining foundational engineering experience.
A Silicon Engineer at Google focused on timing constraint optimization.
Can help others by advising on timing constraint generation and flow development.
🚀 Career trajectory
Engineering Intern
Gained foundational experience in engineering principles during an internship at Qualcomm.
✦ Internship
✦ Qualcomm
Silicon Engineer
Currently driving advanced timing constraint methodologies at Google, contributing to high-performance chip designs.
✦ Semiconductor Engineering
✦ Timing Constraints
💪🏻 Superpowers
Precision Timing Constraint Engineering
Ensuring chip performance through meticulous constraint generation and validation.
✦ Develops optimum frontend/backend flows for timing-constraint generation.
✦ Manages constraint validation for RTL and DFT teams.
✦ Improves chip Quality of Results (QOR).
Flow Development & Scripting Mastery
Automating and enhancing semiconductor design processes with expert scripting.
✦ Proficient in TCL and Python for flow development.
✦ Designs and implements efficient engineering flows.
✦ Drives automation for semiconductor workflows.
Collaborative Chip Design Contributor
Fostering teamwork to achieve shared engineering goals.
✦ Works as a positive and collaborative team member.
✦ Utilizes knowledge for optimal engineering results.
✦ Contributes to cross-functional team success.
I'm excited about
✦ Exploring advanced semiconductor design techniques.
✦ Connecting with experts in chip architecture and verification.
✦ Discovering new collaborative opportunities in hardware innovation.
I can help with
✦ Share insights on timing constraint generation best practices.
✦ Advise on scripting and flow development for EDA tools.
✦ Collaborate on optimizing RTL and DFT validation strategies.
I would love your help on
✦ Guidance on emerging trends in chip design methodologies.
✦ Insights into advanced verification strategies.
✦ Opportunities to discuss novel approaches to chip optimization.